SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

D. Sudhaa, Ch. Santhi Ranib, Sreenivasa Rao Ijjadac aAcharya Nagarjuna University, Department of ECE, Nagarjuna Nagar, Guntur, India bDMSSSVH College of Engineering, Department of ECE, India cDepartment of ECE, GITAM University, Visakhapatnam, India

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Continuous scaling of CMOS devices makes the density of Static Random Access memory (SRAM) array size increases. Maintaining high yield in SRAMs becomes more difficult at lower technology nodes, since they are unguarded to the process variations due to the large array size and cell miniaturization, this factor motivates towards the investigation of new techniques and technologies. FinFET technology is the promising technology with which all hurdles of CMOS technology can be overcome. In this paper, a novel 10T SRAM cell has been proposed, and is designed with both CMOS and FinFET technologies and finally the comparisons are made to know the better one. Synopsis TCAD and Cadence Virtuoso tools has been used to carry out SRAM designs.

DOI:10.12693/APhysPolA.135.702 topics: short channel effects, predictive technology models (PTM), SRAM, FinFET, power dissipation