Reducing Leakage Power for SRAM Design Using Sleep Transistor

S. Khandelwala, S. Akasheb and S. Sharmac aResearch Scholar, Department of Electronics & Communication Engineering, RGPV University, Bhopal, M.P, India bResearch Scholar, Department of Electronics & Communication Engineering, Thapar University, Patiala, Punjab, India cDepartment of Electronics & Communication Engineering, Thapar University, Patiala, Punjab, India

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Low power design is the industry buzzword these days in present chip design technologies. Caches occupy around 50% of the total chip area and consume considerable amount of power. This project's focus is to reduce leakage power consumption of an 8 kbit SRAM by employing techniques like power gating. The main technique used in power gating is the use of sleep transistor. In our design we have chosen a stack-based implementation.

DOI: 10.12693/APhysPolA.123.185 PACS numbers: 85.40.-e