High Quality Gate Insulator/GaN Interface for Enhancement-Mode Field Effect Transistor

A. Taubea, b, R. Kruszkaa, M. Borysiewicza, S. Gierałtowskac, E. Kamińskaa and A. Piotrowskaa aInstitute of Electron Technology, al. Lotników 32/46, 02-668 Warsaw, Poland bInstitute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland cInstitute of Physics, Polish Academy of Sciences, al. Lotników 32/46, 02-668 Warsaw, Poland

Full Text PDF

The capacitance-voltage measurements were applied for characterization of the semiconductor/dielectric interface of GaN MOS capacitors with SiO2 and HfO2/SiO2 gate stacks. From the Terman method low density of interface traps (Dit ≈ 1011 eV-1 cm-2) at SiO2/GaN interface was calculated for as-deposited samples. Samples with HfO2/SiO2 gate stacks have higher density of interface traps as well as higher density of mobile charge and effective charge in the dielectric layers. High quality of SiO2/GaN interface shows applicability of SiO2 as a gate dielectric in GaN MOSFET transistors.

DOI: 10.12693/APhysPolA.120.A-22 PACS numbers: 77.55.dj, 77.22.Ch, 73.40.Qv, 81.15.Gh, 81.15.Cd