Study of Stability Diagrams of Codoped Silicon Nano-Transistors |
| R. Asaia, S. Masuia, R.S. Străteanub, S. Miyagawaa, D. Morarua, b, c
aGraduate School of Integrated Science and Technology, Faculty of Engineering, Shizuoka University, 3-5-1 Johoku, Chuo-ku, Hamamatsu, Shizuoka-ken 432-8011, Japan bFaculty of Engineering, Shizuoka University, 3-5-1 Johoku, Chuo-ku, Hamamatsu, Shizuoka-ken 432-8011, Japan cResearch Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Chuo-ku, Hamamatsu, Shizuoka-ken 432-8011, Japan |
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| This study provides insights into the behavior of nanoscale silicon-on-insulator transistor with codoped channels, in particular at low temperatures. The goal is to compare the stability diagrams (plots of current as a function of gate voltage and source-drain bias) for several devices fabricated in the same batch, but having different designed channel widths. For the narrower device, a simple stability diagram containing a small number of Coulomb diamonds is observed, while for the wider device, a relatively more complex set of overlapped Coulomb diamonds indicates the presence of a larger number of quantum dots. Here, it is also shown how applying a vertical electric field by using the substrate voltage can significantly change the current paths in such devices. |
DOI:10.12693/APhysPolA.146.655 topics: single-electron transistor, silicon-on-insulator, Coulomb blockade, stability diagram |