Barriers in Miniaturization of Electronic Devices and the Ways to Overcome Them - from a Planar to 3D Device Architecture
M. Godlewski a,b, E. Guziewicz a, S. Gierałtowska a, G. Łuka a, T. Krajewski a, Ł. Wachnicki a and K. Kopalko a
a Institute of Physics, Polish Academy of Sciences, al. Lotników 32/46, 02-668 Warsaw, Poland
b Dept. of Mathematics and Natural Sciences, College of Science, Cardinal Stefan Wyszyński University, Warsaw, Poland
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We witness a new revolution in electronic industry - a new generation of integrated circuits uses as a gate isolator HfO2. This high-k oxide was deposited by the atomic layer deposition technique. The atomic layer deposition, due to a high conformality of deposited films and low growth temperature, has a large potential to be widely used not only for the deposition of high-k oxides, but also of materials used in solar cells and semiconductor/organic material hybrid structures. This opens possibilities of construction of novel memory devices with 3D architecture, photovoltaic panels of the third generation and stable in time organic light emitting diodes as discussed in this work.
DOI: 10.12693/APhysPolA.116.S-19
PACS numbers: 85.35.-p, 73.40.Lq, 73.40.Qv, 81.05.Dz, 81.15.-z,